Field of the Disclosure
The present invention is directed to chip packaging, specifically to embedded chips.
Description of the Related Art
Embedding chips within the interposers to the outside world enables shrinking the chip package, shortening the connections to the outside world, offers cost savings by simpler manufacturing that eliminates die to substrate assembly processes and potentially has increased reliability.
Essentially, the concept of embedding active components such as analog, digital and MEMS chips involves the construction of chip support structures or substrates, having vias around the chip.
One way of achieving embedded chips is to fabricate chip support structures onto the chip array on the wafer where the circuitry of the support structure is larger than the die unit size. This is known as Fan Out Wafer Layer Packaging (FOWLP). Although the size of silicon wafers is growing, expensive material sets and manufacturing process are still limiting the diameter size to 12″, thereby limiting the number of FOWLP units one can place on the wafer. Despite the fact that 18″ wafers are under consideration, the investment required, materials sets and equipment are still unknown. The limited number of chip support structures that may be processed at one time increases the unit cost of FOWLP, and make it too expensive for markets requiring highly competitive pricing, such as wireless communication, home appliances and automotive markets.
FOWLP also represents a performance limitation since the metal features placed over the silicon wafer as fan-out or fan-in circuitry are limited in thickness to a few microns. This creates electrical resistance challenges.
An alternative fabrication route involves sectioning the wafer to separate the chips and embedding the chips within a panel consisting of dielectric layers with copper interconnects. One advantage of this alternative route is that the panels may be very much larger with very many more chips embedded in a single process. For example, whereas for example, a 12″ wafer enables 2,500 FOWLP chips having dimensions of 5 mm×5 mm to be processed in one go, current panels used the applicant, Zhuhai Access, are 25″×21″, enabling 10,000 chips to be processed in one go. Since the price of processing such panels is significantly cheaper than on wafer processing, and since the throughput per panel is 4× higher than throughput on wafer, the unit cost can drop significantly, thereby opening new markets.
In both technologies, the line spacing and the width of the tracks used in industry are shrinking over time, with 15 micron going down to 10 microns being standard on panels and 5 microns going down to 2 microns on wafers.
The advantages of embedding are many. First level assembly costs, such as wire bonding, flip chip or SMD (Surface Mount Devices) soldering, are eliminated. The electrical performance is improved since the die and substrate are seamlessly connected within a single product. The packaged dies are thinner, giving an improved form factor, and the upper surface of the embedded die package is freed up for other uses including stacked die and PoP (Package on Package) technologies.
In both FOWLP and Panel based embedded die technologies, the chips are packaged as an array (on wafer or panel), and, once fabricated, are separated by dicing. Yang (US 2008/0157336) discloses an on-wafer packaging method. A grid with conductive vias is placed onto and bonded with a wafer with chips thereupon. The wafer is subsequently diced.
The methodology of Yang has a problem in that differences in coefficient of thermal expansion (CTE) between silicon, metals and polymers results in a need for a dielectric layer under the re-distribution layer (RDL) and also a protective layer thereover. This increases costs and requires the creation of a via in the dielectric layer under the redistribution layer to allow metal contact between the Die pads and the RDL, complicating and reducing yields of the manufacturing process due to the need for precise alignment between the via and the die pad.
Fabricating the vias required by Yang requires complex laser drilling or photolithography to expose the extra dielectric layer over the die. This requires an alignment step that reduces yield, increases unit cost and limits the range of dies that may be packaged in this manner. It will be appreciated that as the die pad contacts become smaller the dielectric via needs to be scaled down accordingly to allow alignment without the via failing. Furthermore, Yang's extra dielectric layer covers both the die terminals and the PCB connection terminals requiring that this dielectric layer conform to z-axis topographies that are different in scale. For example, in the PCB frame the dielectric layer is typically required to cover Cu pad terminals that are 10 to 20 microns diameter, while the terminals of the die itself which also need to be covered are typically an order of magnitude smaller and are only 1 to 2 microns thick. Since the dielectric layer needs to be at least 10 microns above the PCB pad terminals to cover their topography, it will be 20 microns above the smaller Die terminals. To create vias having diameters that are less than 50 microns in diameter in a dielectric layer that is 10 to 20 micron thick is technologically challenging. Reliability requirements would force the die terminals to remain larger than 50 um+10 um (for best alignment) requiring 60 micron diameter die pads. Since both die geometries and the size of their terminals are ever shrinking, the limitation of the structure proposed by Yang is clear.
Thus in many cases, the via size in the extra dielectric layer will have a minimal diameter due to process concerns, thereby limiting the application of this structure to wide range of dies.
Yang (US 2008/0157336) Yang discloses a package structure having a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under the die and filled in the gap between the die and side wall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a redistribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.
Pending Patent Publication No. US 2015/279,814 to the present applicant, titled “embedded chips” describes a structure comprising at least one die positioned in a through hole within a frame of a first polymer matrix, the die being embedded in a second polymer matrix and surrounded by matrix, wherein the die is positioned with its terminals on a lower surface such that said lower surface of said die is coplanar with a lower surface of the frame, The frame is thicker than the die, and wherein the die is surrounded on all but lower face with a packaging material a comprising the second polymer matrix, wherein a first feature layer of conductor pads is deposited onto the coplanar lower surfaces of the die and frame. Despite the advantages of the embedded chips described in US 2015/279,814, such chips have poor heat dissipation since the upper side of the die that is opposite to the side with terminals is covered with the packaging material which has poor heat conductivity.